2.3 Synchronous Operation of the Signal Routing Port (Clock)

The Signal Routing Port module contains a flip-flop in each signal routing port pin to allow an optional synchronous operation. This flip-flop is disabled by default, allowing for an asynchronous path between the input and output of the signal routing port pin. The PORTWDF Data Flip Flop Register is used to individually enable or disable synchronous operation on each signal routing port pin.

When enabled, a flip-flop is introduced in the path between the input and output of a signal routing port pin, as shown in Figure 2-3. This allows the signal routing port pin to hold the value of the input in between clock pulses and behave synchronously with the clock selected using the PORTWCLK register. The CLKEN bit in the PORTWCON register enables the selected clock source.

The synchronous operation of the Signal Routing Port is fundamental to using the module as a shift register or hardware state machine. Refer to Hardware State Machines and Shift Register Operation for application use cases.