19.14.1 Timer Register
| Name: | TMRx |
| Offset: | 0xFCD,0xFC7,0xFC1,0xF2E |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TMRx[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TMRx[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – TMRx[15:0] Timer Register Value
Note: The individual bytes in this
multibyte register can be accessed with the following register names:
- TMRxH: Accesses the high byte TMRx[15:8]
- TMRxL: Accesses the low byte TMRx[7:0]
| Reset States: |
|