19.14.5 TMRxCLK

Timer Clock Source Selection Register

Name:	TMRxCLK
Offset:	0xFD2,0xFCC,0xFC6,0xF33


Bit	7	6	5	4	3	2	1	0
					CS[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:0 – CS[3:0] Timer Clock Source Selection bits


CS	Clock Source
CS	Timer1	Timer3	Timer5	Timer7
`1111-1101`	Reserved	Reserved	Reserved	Reserved
`1100`	TMR7 overflow	TMR7 overflow	TMR7 overflow	Reserved
`1011`	TMR5 overflow	TMR5 overflow	Reserved	TMR5 overflow
`1010`	TMR3 overflow	Reserved	TMR3 overflow	TMR3 overflow
`1001`	Reserved	TMR1 overflow	TMR1 overflow	TMR1 overflow
`1000`	TMR0 overflow	TMR0 overflow	TMR0 overflow	TMR0 overflow
`0111`	CLKREF	CLKREF	CLKREF	CLKREF
`0110`	SOSC	SOSC	SOSC	SOSC
`0101`	MFINTOSC (500 kHz)	MFINTOSC (500 kHz)	MFINTOSC (500 kHz)	MFINTOSC (500 kHz)
`0100`	LFINTOSC	LFINTOSC	LFINTOSC	LFINTOSC
`0011`	HFINTOSC	HFINTOSC	HFINTOSC	HFINTOSC
`0010`	Fosc	Fosc	Fosc	Fosc
`0001`	Fosc/4	Fosc/4	Fosc/4	Fosc/4
`0000`	T1CKIPPS	T3CKIPPS	T5CKIPPS	T7CKIPPS

Reset States:

POR/BOR = 0000

All Other Resets = uuuu

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