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64-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology
Description
Core Features
Memory
Operating Characteristics
Power-Saving Operation Modes
eXtreme Low-Power (XLP) Features
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
PIC18(L)F65/66K40 Family Types
Pin Diagrams
Pin Allocation Tables
1 Device Overview
1.1 New Core Features
1.2 Other Special Features
1.3 Details on Individual Family Members
1.4 Register and Bit Naming Conventions
2 Guidelines for Getting Started with PIC18(L)F65/66K40 Microcontrollers
2.1 Basic Connection Requirements
2.2 Power Supply Pins
2.3 Master Clear (MCLR) Pin
2.4 In-Circuit Serial Programming™ (ICSP™) Pins
2.5 External Oscillator Pins
2.6 Unused I/Os
3 Device Configuration
3.1 Configuration Words
3.2 Code Protection
3.3 Write Protection
3.4 User ID
3.5 Device ID and Revision ID
3.6 Register Summary - Configuration Words
3.7 Register Definitions: Configuration Words
3.8 Register Summary - Device and Revision
3.9 Register Definitions: Device and Revision
4 OSC - Oscillator Module
4.1 Overview
4.2 Clock Source Types
4.3 Clock Switching
4.4 Fail-Safe Clock Monitor
4.5 Register Summary - OSC
4.6 Register Definitions: Oscillator Control
5 REFCLK - Reference Clock Output Module
5.1 Clock Source
5.2 Programmable Clock Divider
5.3 Selectable Duty Cycle
5.4 Operation in Sleep Mode
5.5 Register Summary - Reference CLK
5.6 Register Definitions: Reference Clock
6 Power-Saving Operation Modes
6.1 Doze Mode
6.2 Sleep Mode
6.3 Peripheral Operation in Power-Saving Modes
6.4 Register Summary - Power Savings Control
6.5 Register Definitions: Power Savings Control
7 PMD - Peripheral Module Disable
7.1 Disabling a Module
7.2 Enabling a Module
7.3 Register Summary - PMD
7.4 Register Definitions: Peripheral Module Disable
8 Resets
8.1 Power-on Reset (POR)
8.2 Brown-out Reset (BOR)
8.3 Low-Power Brown-out Reset (LPBOR)
8.4 MCLR Reset
8.5 Windowed Watchdog Timer (WWDT) Reset
8.6 RESET Instruction
8.7 Stack Overflow/Underflow Reset
8.8 Programming Mode Exit
8.9 Power-up Timer (PWRT)
8.10 Start-up Sequence
8.11 Determining the Cause of a Reset
8.12 Power Control (PCON0) Register
8.13 Register Summary - BOR Control and Power Control
8.14 Register Definitions: Power Control
9 WWDT - Windowed Watchdog Timer
9.1 Independent Clock Source
9.2 WWDT Operating Modes
9.3 Time-out Period
9.4 Watchdog Window
9.5 Clearing the WWDT
9.6 Operation During Sleep
9.7 Register Summary - WDT Control
9.8 Register Definitions: Windowed Watchdog Timer Control
10 Memory Organization
10.1 Program Memory Organization
10.2 PIC18 Instruction Cycle
10.3 Data Memory Organization
10.4 Data Addressing Modes
10.5 Data Memory and the Extended Instruction Set
10.6 PIC18 Instruction Execution and the Extended Instruction Set
10.7 Register Summary - Memory and Status
10.8 Register Definitions: Memory and Status
11 NVM - Nonvolatile Memory Control
11.1 Program Flash Memory
11.2 User ID, Device ID and Configuration Word Access
11.3 Data EEPROM Memory
11.4 Register Summary - NVM Control
11.5 Register Definitions: Nonvolatile Memory
12 8x8 Hardware Multiplier
12.1 Introduction
12.2 Operation
12.3 Register Summary - 8x8 Hardware Multiplier
12.4 Register Definitions: 8x8 Hardware Multiplier
13 CRC - Cyclic Redundancy Check Module with Memory Scanner
13.1 CRC Module Overview
13.2 CRC Functional Overview
13.3 CRC Polynomial Implementation
13.4 CRC Data Sources
13.5 CRC Check Value
13.6 CRC Interrupt
13.7 Configuring the CRC
13.8 Program Memory Scan Configuration
13.9 Scanner Interrupt
13.10 Scanning Modes
13.11 Register Summary - CRC
13.12 Register Definitions: CRC and Scanner Control
14 Interrupts
14.1 Midrange Compatibility
14.2 Interrupt Priority
14.3 Interrupt Response
14.4 INTCON Registers
14.5 PIR Registers
14.6 PIE Registers
14.7 IPR Registers
14.8 INTn Pin Interrupts
14.9 TMR0 Interrupt
14.10 Interrupt-on-Change
14.11 Context Saving During Interrupts
14.12 Register Summary - Interrupt Control
14.13 Register Definitions: Interrupt Control
15 I/O Ports
15.1 I/O Priorities
15.2 PORTx Registers
15.3 Register Summary - Input/Output
15.4 Register Definitions: Port Control
16 Interrupt-on-Change
16.1 Features
16.2 Overview
16.3 Block Diagram
16.4 Enabling the Module
16.5 Individual Pin Configuration
16.6 Interrupt Flags
16.7 Clearing Interrupt Flags
16.8 Operation in Sleep
16.9 Register Summary - Interrupt-on-Change
16.10 Register Definitions: Interrupt-on-Change Control
17 PPS - Peripheral Pin Select Module
17.1 PPS Inputs
17.2 PPS Outputs
17.3 Bidirectional Pins
17.4 PPS Lock
17.5 PPS One-Way Lock
17.6 Operation During Sleep
17.7 Effects of a Reset
17.8 Register Definitions: PPS Input and Output Selection
18 TMR0 - Timer0 Module
18.1 Timer0 Operation
18.2 Clock Selection
18.3 Timer0 Output and Interrupt
18.4 Operation During Sleep
18.5 Register Summary - Timer0
18.6 Register Definitions: Timer0 Control
19 TMR1 - Timer1 Module with Gate Control
19.1 Timer1 Operation
19.2 Clock Source Selection
19.3 Timer1 Prescaler
19.4 Secondary Oscillator
19.5 Timer1 Operation in Asynchronous Counter Mode
19.6 Timer1 16-Bit Read/Write Mode
19.7 Timer1 Gate
19.8 Timer1 Interrupt
19.9 Timer1 Operation During Sleep
19.10 CCP Capture/Compare Time Base
19.11 CCP Special Event Trigger
19.12 Peripheral Module Disable
19.13 Register Summary - Timer1
19.14 Register Definitions: Timer1
20 TMR2 - Timer2 Module
20.1 Timer2 Operation
20.2 Timer2 Output
20.3 External Reset Sources
20.4 Timer2 Interrupt
20.5 PSYNC Bit
20.6 CSYNC Bit
20.7 Operating Modes
20.8 Operation Examples
20.9 Timer2 Operation During Sleep
20.10 Register Summary - Timer2
20.11 Register Definitions: Timer2 Control
21 Capture/Compare/PWM Module
21.1 CCP Module Configuration
21.2 Capture Mode
21.3 Compare Mode
21.4 PWM Overview
21.5 Register Summary - CCP Control
21.6 Register Definitions: CCP Control
22 (PWM) Pulse-Width Modulation
22.1 Fundamental Operation
22.2 PWM Output Polarity
22.3 PWM Period
22.4 PWM Duty Cycle
22.5 PWM Resolution
22.6 Operation in Sleep Mode
22.7 Changes in System Clock Frequency
22.8 Effects of Reset
22.9 Setup for PWM Operation Using PWMx Output Pins
22.10 Setup for PWM Operation to Other Device Peripherals
22.11 Register Summary - Registers Associated with PWM
22.12 Register Definitions: PWM Control
23 ZCD - Zero-Cross Detection Module
23.1 External Resistor Selection
23.2 ZCD Logic Output
23.3 ZCD Logic Polarity
23.4 ZCD Interrupts
23.5 Correction for ZCPINV Offset
23.6 Handling VPEAK Variations
23.7 Operation During Sleep
23.8 Effects of a Reset
23.9 Disabling the ZCD Module
23.10 Register Summary - ZCD Control
23.11 Register Definitions: ZCD Control
24 CWG - Complementary Waveform Generator
24.1 Fundamental Operation
24.2 Operating Modes
24.3 Start-up Considerations
24.4 Clock Source
24.5 Selectable Input Sources
24.6 Output Control
24.7 Dead-Band Control
24.8 Rising Edge and Reverse Dead Band
24.9 Falling Edge and Forward Dead Band
24.10 Dead-Band Jitter
24.11 Auto-Shutdown
24.12 Operation During Sleep
24.13 Configuring the CWG
24.14 Register Summary - CWG Control
24.15 Register Definitions: CWG Control
25 SMT - Signal Measurement Timer
25.1 SMT Operation
25.2 Register Summary - SMT Control
25.3 Register Definitions: SMT Control
26 DSM - Data Signal Modulator Module
26.1 DSM Operation
26.2 Modulator Signal Sources
26.3 Carrier Signal Sources
26.4 Carrier Synchronization
26.5 Carrier Source Polarity Select
26.6 Programmable Modulator Data
26.7 Modulated Output Polarity
26.8 Operation in Sleep Mode
26.9 Effects of a Reset
26.10 Peripheral Module Disable
26.11 Register Summary - DSM
26.12 Register Definitions: Modulation Control
27 MSSP - Host Synchronous Serial Port Module
27.1 SPI Mode Overview
27.2 SPI Mode Operation
27.3 I2C Mode Overview
27.4 I2C Mode Operation
27.5 I2C Client Mode Operation
27.6 I2C Host Mode
27.7 Baud Rate Generator
27.8 Register Summary - MSSP Control
27.9 Register Definitions: MSSP Control
28 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
28.1 EUSART Asynchronous Mode
28.2 EUSART Baud Rate Generator (BRG)
28.3 EUSART Synchronous Mode
28.4 EUSART Operation During Sleep
28.5 Register Summary - EUSART
28.6 Register Definitions: EUSART Control
29 FVR - Fixed Voltage Reference
29.1 Independent Gain Amplifiers
29.2 FVR Stabilization Period
29.3 Register Summary - FVR
29.4 Register Definitions: FVR Control
30 Temperature Indicator Module
30.1 Circuit Operation
30.2 Minimum Operating VDD
30.3 Temperature Output
30.4 ADC Acquisition Time
31 (DAC) 5-Bit Digital-to-Analog Converter Module
31.1 Output Voltage Selection
31.2 Ratiometric Output Level
31.3 DAC Voltage Reference Output
31.4 Operation During Sleep
31.5 Effects of a Reset
31.6 Register Summary - DAC Control
31.7 Register Definitions: DAC Control
32 ADCC - Analog-to-Digital Converter with Computation Module
32.1 ADC Configuration
32.2 ADC Operation
32.3 ADC Acquisition Requirements
32.4 Capacitive Voltage Divider (CVD) Features
32.5 Computation Operation
32.6 Register Summary - ADC Control
32.7 Register Definitions: ADC Control
33 CMP - Comparator Module
33.1 Comparator Overview
33.2 Comparator Control
33.3 Comparator Hysteresis
33.4 Operation with Timer1 Gate
33.5 Comparator Interrupt
33.6 Comparator Positive Input Selection
33.7 Comparator Negative Input Selection
33.8 Comparator Response Time
33.9 Analog Input Connection Considerations
33.10 CWG1 Auto-Shutdown Source
33.11 ADC Auto-Trigger Source
33.12 Even Numbered Timers Reset
33.13 Operation in Sleep Mode
33.14 Register Summary - Comparator
33.15 Register Definitions: Comparator Control
34 HLVD - High/Low-Voltage Detect
34.1 Operation
34.2 Setup
34.3 Current Consumption
34.4 HLVD Start-up Time
34.5 Applications
34.6 Operation During Sleep
34.7 Operation During Idle and Doze Modes
34.8 Effects of a Reset
34.9 Register Summary - HLVD
34.10 Register Definitions: HLVD Control
35 Register Summary
36 ICSP™ - In-Circuit Serial Programming™
36.1 High-Voltage Programming Entry Mode
36.2 Low-Voltage Programming Entry Mode
36.3 Common Programming Interfaces
37 Instruction Set Summary
37.1 Standard Instruction Set
37.2 Extended Instruction Set
38 Development Support
38.1 MPLAB® X Integrated Development Environment Software
38.2 MPLAB® XC Compilers
38.3 MPASM™ Assembler
38.4 MPLINK™ Object Linker/MPLIB™ Object Librarian
38.5 MPLAB® Assembler, Linker and Librarian for Various Device Families
38.6 MPLAB® X SIM Software Simulator
38.7 MPLAB® REAL ICE™ In-Circuit Emulator System
38.8 MPLAB® ICD 3 In-Circuit Debugger System
38.9 PICkit™ 3 In-Circuit Debugger/Programmer
38.10 MPLAB® PM3 Device Programmer
38.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
38.12 Third-Party Development Tools
39 Electrical Specifications
39.1 Absolute Maximum Ratings(†)
39.2 Standard Operating Conditions
39.3 DC Characteristics
39.4 AC Characteristics
40 DC and AC Characteristics Graphs and Tables
40.1 Graphs
41 Packaging Information
41.1 Package Details
42 Revision History
Microchip Information
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