3.7.2 CONFIG2
Supervisor
Note: BORV - The
higher voltage setting is recommended for operation at or above 16 MHz.
| Name: | CONFIG2 |
| Offset: | 0x300002 |
Configuration Word 2
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| XINST | DEBUG | STVREN | PPS1WAY | ZCD | BORV[1:0] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BOREN[1:0] | LPBOREN | PWRTE | MCLRE | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 1 | 1 | 1 | 1 | ||||
Bit 15 – XINST Extended Instruction Set Enable bit
| Value | Description |
|---|---|
| 1 | Extended Instruction Set and Indexed Addressing mode disabled (Legacy mode) |
| 0 | Extended Instruction Set and Indexed Addressing mode enabled |
Bit 13 – DEBUG Debugger Enable bit
| Value | Description |
|---|---|
| 1 | Background debugger disabled |
| 0 | Background debugger enabled |
Bit 12 – STVREN Stack Overflow/Underflow Reset Enable bit
| Value | Description |
|---|---|
| 1 | Stack Overflow or Underflow will cause a Reset |
| 0 | Stack Overflow or Underflow will not cause a Reset |
Bit 11 – PPS1WAY PPSLOCKED bit One-Way Set Enable bit
| Value | Description |
|---|---|
| 1 | The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all future changes to PPS registers are prevented |
| 0 | The PPSLOCKED bit can be set and cleared as needed (provided an unlocking sequence is executed) |
Bit 10 – ZCD ZCD Disable bit
| Value | Description |
|---|---|
| 1 | ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON |
| 0 | ZCD always enabled, PMDx[ZCDMD] bit is ignored |
Bits 9:8 – BORV[1:0] Brown-out Reset Voltage Selection bit
PIC18F device:
PIC18LF device:
| Value | Description |
|---|---|
| 11 | Brown-out Reset Voltage (VBOR) set to 2.45V |
| 10 | Brown-out Reset Voltage (VBOR) set to 2.45V |
| 01 | Brown-out Reset Voltage (VBOR) set to 2.7V |
| 00 | Brown-out Reset Voltage (VBOR) set to 2.85V |
| Value | Description |
|---|---|
| 11 | Brown-out Reset Voltage (VBOR) set to 1.90V |
| 10 | Brown-out Reset Voltage (VBOR) set to 2.45V |
| 01 | Brown-out Reset Voltage (VBOR) set to 2.7V |
| 00 | Brown-out Reset Voltage (VBOR) set to 2.85V |
Bits 7:6 – BOREN[1:0] Brown-out Reset Enable bits
When enabled, Brown-out Reset Voltage (VBOR) is set by BORV bit
| Value | Description |
|---|---|
| 11 | Brown-out Reset enabled, SBOREN bit is ignored |
| 10 | Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored |
| 01 | Brown-out Reset enabled according to SBOREN |
| 00 | Brown-out Reset disabled |
Bit 5 – LPBOREN Low-Power BOR Enable bit
| Value | Description |
|---|---|
| 1 | Low-Power Brown-out Reset is disabled |
| 0 | Low-Power Brown-out Reset is enabled |
Bit 1 – PWRTE Power-up Timer Enable bit
| Value | Description |
|---|---|
| 1 | PWRT disabled |
| 0 | PWRT enabled |
Bit 0 – MCLRE Master Clear (MCLR) Enable bit
| Value | Name | Description |
|---|---|---|
| x | If LVP =
1 | RE3 pin function is MCLR |
| 1 | If LVP =
0 | MCLR pin is MCLR |
| 0 | If LVP =
0 | MCLR pin function is port defined function |