6.5.2 CPUDOZE

Doze and Idle Register

Note:

When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.

Name:	CPUDOZE
Offset:	0xE42


Bit	7	6	5	4	3	2	1	0
	IDLEN	DOZEN	ROI	DOE		DOZE[2:0]
Access	R/W	R/W/HC/HS	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0

Bit 7 – IDLEN Idle Enable bit

Reset States:

POR/BOR = 0

All Other Resets = u

Value	Description
1	A `SLEEP` instruction inhibits the CPU clock, but not the peripheral clock(s)
0	A `SLEEP` instruction places the device into full Sleep mode

Bit 6 – DOZEN

Doze Enable bit⁽¹⁾

Value	Description
1	The CPU executes instruction cycles according to DOZE setting
0	The CPU executes all instruction cycles (fastest, highest power operation)

Bit 5 – ROI Recover-On-Interrupt bit

Value	Description
1	Entering the Interrupt Service Routine (ISR) makes DOZEN = `0`, bringing the CPU to full-speed operation
0	Interrupt entry does not change DOZEN

Bit 4 – DOE Doze-On-Exit bit

Value	Description
1	Executing RETFIE makes DOZEN = `1`, bringing the CPU to reduced speed operation
0	RETFIE does not change DOZEN

Bits 2:0 – DOZE[2:0] Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles

Value	Description
111	1:256
110	1:128
101	1:64
100	1:32
011	1:16
010	1:8
001	1:4
000	1:2

When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.

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