17.1 PPS Inputs

Each peripheral has a PPS register with which the input pin to the peripheral is selected. Although each peripheral has its own PPS input selection register, the selections are identical for every peripheral, as shown in xxxPPS. Not all ports are available for input, as shown in the “PPS Input Selection Register Details” table.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = INT for the INTPPS register.
Table 17-1. PPS Input Selection Register Details
PeripheralPPS Input RegisterDefault Pin Selection
 at PORRegister Reset Value
 at PORPORT From Which Input Is Available
Interrupt 0INT0PPSRB00x08AB
Interrupt 1INT1PPSRB10x09BC
Interrupt 2INT2PPSRB20x0ABD
Interrupt 3INT3PPSRB30x0BBE
Timer0 ClockT0CKIPPSRA40x04AB
Timer1 ClockT1CKIPPSRC00x10ACD
Timer1 GateT1GPPSRB50x0DBC
Timer3 ClockT3CKIPPSRB50x0DBC
Timer3 GateT3GPPSRA50x05AC
Timer5 ClockT5CKIPPSRD10x19ADE
Timer5 GateT5GPPSRG40x34BEG
Timer7 ClockT7CKIPPSRG40x34AEG
Timer7 GateT7GPPSRD10x19BDE
Timer2 ClockT2INPPSRA10x01AC
Timer4 ClockT4INPPSRE40x24BE
Timer6 ClockT6INPPSRC10x11BC
Timer8 ClockT8INPPSRA00x00AE
ADC Conversion TriggerADACTPPSRH10x39BCH
CCP1CCP1PPSRE50x25BCE
CCP2CCP2PPSRE40x24BCE
CCP3CCP3PPSRE60x26BCE
CCP4CCP4PPSRG30x33BEG
CCP5CCP5PPSRG40x34BEG
SMT1 WindowSMT1WINPPSRE60x26ACE
SMT1 SignalSMT1SIGPPSRE70x27BCE
SMT2 WindowSMT2WINPPSRE60x26ACG
SMT2 SignalSMT2SIGPPSRE70x27BCG
CWGCWG1PPSRC20x12AC
DSM Carrier LowMDCARLPPSRD30x1BADH
DSM Carrier HighMDCARHPPSRD40x1CADH
DSM SourceMDSRCPPSRD50x1DADH
MSSP1 ClockSSP1CLKPPSRC30x13BC
MSSP1 DataSSP1DATPPSRC40x14BC
MSSP1 Slave SelectSSP1SSPPSRF70x2FBF
MSSP2 ClockSSP2CLKPPSRD60x1EBD
MSSP2 DataSSP2DATPPSRD50x1DBD
MSSP2 Slave SelectSSP2SSPPSRD70x1FBD
EUSART1 ReceiveRX1PPSRC70x17BCD
EUSART1 ClockCK1PPSRC60x16BCD
EUSART2 ReceiveRX2PPSRG20x32BDG
EUSART2 ClockCK2PPSRG10x31BDG
EUSART3 ReceiveRX3PPSRE10x21BE
EUSART3 ClockCK3PPSRE00x20BE
EUSART4 ReceiveRX4PPSRC10x11BC
EUSART4 ClockCK4PPSRC00x10BC
EUSART5 ReceiveRX5PPSRE30x23BEG
EUSART5 ClockCK5PPSRE20x22BEG
Note:
  1. Some pads are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register.
Table 17-2. PPS Input Register Values
Desired Input PinValue to Write to Register
RH311 1011
RH211 1010
RH111 1001
RH011 1000
RG711 0111
RG611 0110
RG511 0101
RG411 0100
RG311 0011
RG211 0010
RG111 0001
RG011 0000
RF710 1111
RF610 1110
RF510 1101
RF410 1100
RF310 1011
RF210 1010
RF110 1001
RF010 1000
RE710 0111
RE610 0110
RE510 0101
RE410 0100
RE310 0011
RE210 0010
RE110 0001
RE010 0000
RD701 1111
RD601 1110
RD501 1101
RD401 1100
RD301 1011
RD201 1010
RD101 1001
RD001 1000
RC701 0111
RC601 0110
RC501 0101
RC401 0100
RC301 0011
RC201 0010
RC101 0001
RC001 0000
RB700 1111
RB600 1110
RB500 1101
RB400 1100
RB300 1011
RB200 1010
RB100 1001
RB000 1000
RA700 0111
RA600 0110
RA500 0101
RA400 0100
RA300 0011
RA200 0010
RA100 0001
RA000 0000