27.8 Register Summary - MSSP Control
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x0ED4 | Reserved | |||||||||
| 0x0ED5 | SSP2BUF | 7:0 | BUF[7:0] | |||||||
| 0x0ED6 | SSP2ADD | 7:0 | ADD[7:0] | |||||||
| 0x0ED7 | SSP2MSK | 7:0 | MSK[6:0] | MSK0 | ||||||
| 0x0ED8 | SSP2STAT | 7:0 | SMP | CKE | D/A | P | S | R/W | UA | BF |
| 0x0ED9 | SSP2CON1 | 7:0 | WCOL | SSPOV | SSPEN | CKP | SSPM[3:0] | |||
| 0x0EDA | SSP2CON2 | 7:0 | GCEN | ACKSTAT | ACKDT | ACKEN | RCEN | PEN | RSEN | SEN |
| 0x0EDB | SSP2CON3 | 7:0 | ACKTIM | PCIE | SCIE | BOEN | SDAHT | SBCDE | AHEN | DHEN |
0x0EDC ... 0x0F90 | Reserved | |||||||||
| 0x0F91 | SSP1BUF | 7:0 | BUF[7:0] | |||||||
| 0x0F92 | SSP1ADD | 7:0 | ADD[7:0] | |||||||
| 0x0F93 | SSP1MSK | 7:0 | MSK[6:0] | MSK0 | ||||||
| 0x0F94 | SSP1STAT | 7:0 | SMP | CKE | D/A | P | S | R/W | UA | BF |
| 0x0F95 | SSP1CON1 | 7:0 | WCOL | SSPOV | SSPEN | CKP | SSPM[3:0] | |||
| 0x0F96 | SSP1CON2 | 7:0 | GCEN | ACKSTAT | ACKDT | ACKEN | RCEN | PEN | RSEN | SEN |
| 0x0F97 | SSP1CON3 | 7:0 | ACKTIM | PCIE | SCIE | BOEN | SDAHT | SBCDE | AHEN | DHEN |