3.1.2 XCVR Configuration

The transceiver configuration for the DisplayPort Rx implementation is shown in the following figure. The transceiver is configured in Rx only mode in a 4 Lane configuration. The Lanes 0,1, 2, and 3 carry DisplayPort Receiver output data.
Figure 3-4. Transceiver Interface Configuration—Instance 1
The transceiver configuration for the HDMI TX implementation is shown in the following figure. The transceiver is configured in Tx only mode in a 4 Lane configuration. The clock signal is carried by LANE0, while Lanes 1, 2, and 3 carry DisplayPort Transmitter output data.
Figure 3-5. Transceiver Interface Configuration—Instance 2