3.4.4.49 DDR3PHY BIST Address 2
Register
| Name: | DDR3PHY_BISTAR2 |
| Offset: | 0x11C |
| Reset: | 0x7FFFFFFF |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | BMBANK[2:0] | BMROW[15:12] | |
| Access | | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | BMROW[11:4] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | BMROW[3:0] | BMCOL[11:8] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | BMCOL[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 30:28 – BMBANK[2:0] BIST Maximum Bank Address
Specifies the maximum SDRAM bank
address to be used during BIST before the address increments to the next
rank.
Bits 27:12 – BMROW[15:0] BIST Maximum Row Address
Specifies the maximum SDRAM row
address to be used during BIST before the address increments to the next
bank.
Bits 11:0 – BMCOL[11:0] BIST Maximum Column Address
Specifies the maximum SDRAM column
address to be used during BIST before the address increments to the next
row.
