11.1.8.16 MIPI D-PHY Characteristics
The device complies with the protocol and electrical specifications of the following standards:
- MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2), Version 1.2
- MIPI Alliance Specification for D-PHY, Version 1.2
| Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|
| VDDIN33 | Supply voltage range (VDDIN33)(1) | – | 3.0 | 3.60 | V |
| IDDIN33 | Current consumption (VDDIN33) | HS mode, 2 lanes | – | 10.0 | mA |
| tSTART | Start-up time(2) | – | – | 60 | μs |
| VIN | Recommended input voltage range(2) | On MIPI_CLKx and MIPI_Dx | -50 | 1350 | mV |
| ILEAK | Input leakage current(2) | On MIPI_CLKx and MIPI_Dx | -10 | 10 | µA |
| High-Speed Characteristics | |||||
| VCMRXDC | Input common mode voltage range(1) | – | 70 | 330 | mV |
| VIDTH | Differential input high voltage threshold(2) | – | – | 70 | mV |
| VIDTL | Differential input low voltage threshold(2) | – | -70 | – | mV |
| VIHHS | Input high voltage(2) | – | – | 460 | mV |
| VILHS | Input low voltage(2) | – | -40 |
─ | mV |
| ZID | Differential input impedance(2) | – | 80 | 125 | Ω |
| fCSICK | MIPI_CLKx output frequency(2) | – | 40 | 500 | MHz |
| BRLANE | Bit rate per lane(2) | – | 80 | 1000 | Mbps |
| Low-Power Characteristics | |||||
| VIH | Input high level(2) | – | 880 | – | mV |
| VIL | Input low level(2) | – | – | 550 | mV |
| VHYST | Input hysteresis(2) | – | 25 | – | mV |
| VIHF | Input high fault threshold(2) | – | 450 | – | mV |
| VILF | Input low fault threshold(2) | – | – | 200 | mV |
- This MIPI D-PHY must be powered by the 2.5V regulated output of the VDDOUT25 regulator, which is supplied from VDDIN33.
- Simulation data
