6.3 UART Interface

The ATWINC15x0B supports the Universal Asynchronous Receiver/Transmitter (UART) interface. This interface is intended for debugging purposes only. The UART is available on pins 12 and 19. It is recommended to add test points for these pins. The UART is compatible with the RS-232 standard and the ATWINC15x0B operates as Data Terminal Equipment (DTE). It has a two-pin RXD/TXD interface.

The following is the default configuration for accessing the UART interface of the ATWINC15x0B:
  • Baud rate: 460800
  • Data: 8 bit
  • Parity: None
  • Stop bit: 1 bit
  • Flow control: None

It also has RX and TX FIFOs, which ensure reliable high-speed reception and low software overhead transmission. FIFO size is 4 x 8 for both RX and TX direction. The UART also has status registers showing the number of received characters available in the FIFO and various error conditions, as well the ability to generate interrupts based on these status bits.

An example of the UART receiving or transmitting a single packet is shown in the following figure. This example shows 7-bit data (0x45), odd parity and two stop bits.

Figure 6-4. Example of UART RX or TX Packet