6.2 SPI Slave Interface

The ATWINC15x0B provides a Serial Peripheral Interface (SPI) that operates as an SPI slave. This is the main interface to the host. The SPI slave interface can be used to control and for serial I/O of 802.11 data. The SPI Slave pins are mapped as shown in the following table. The RXD pin is the same as the Master Output, Slave Input (MOSI) and the TXD pin is the same as the Master Input, Slave Output (MISO). The SPI Slave is a full-duplex slave-synchronous serial interface that is available following Reset when pin 9 (SDIO_SPI_CFG) is tied to VDDIO.

Table 6-2. ATWINC15x0B SPI Slave Interface Pin Mapping
Pin NumberPin NameSPI Function
9SDIO_SPI_CFGMust be tied to VDDIO
16SSNActive low slave select
18SPI_SCKSerial clock
13SPI_RXDSerial data receive (MOSI)
17SPI_TXDSerial data transmit (MISO)

When the SPI is not selected, that is, when SSN is high, the SPI interface does not interfere with data transfers between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted data output is buffered, resulting in a high impedance drive onto the serial master receive line.

The SPI slave interface responds to a protocol that allows an external host to read or write any register in the chip as well as initiates DMA transfer.

The SPI slave interface supports four Standard modes as determined by the Clock Polarity (CPOL) and Clock Phase (CPHA) settings. These modes are illustrated in the following table and figure.

Table 6-3. SPI Modes
ModeCPOLCPHA
0(1)00
101
210
311
Note:
  1. The ATWINC15x0 firmware uses SPI MODE 0 to communicate with the host.
Figure 6-2. ATWINC15x0B SPI Slave Clock Polarity and Clock Phase Timing

The red lines in the following figure correspond to Clock Phase = 0 and the blue lines correspond to Clock Phase = 1.

Figure 6-3. ATWINC15x0BSPI Slave Timing Diagram
Table 6-4. ATWINC15x0B SPI Slave Timing Parameters (1)
ParameterSymbolMin.Max.Units
Clock input frequency(2)fSCK—48MHz
Clock low pulse widthtWL4—ns
Clock high pulse widthtWH5—
Clock rise timetLH07
Clock fall timetHL07
TXD output delay(3)tODLY49 from SCK fall
RXD input setup timetISU1—
RXD input hold timetIHD5—
SSN input setup timetSUSSN3—
SSN input hold timetHDSSN5.5—
Note:
  1. Timing is applicable to all the SPI modes.
  2. Maximum clock frequency specified is limited by the SPI slave interface internal design. Actual maximum clock frequency can be lower and depends on the specific PCB layout.
  3. Timing is based on 15 pF output loading. Under all conditions, tLH + tWH + tHL + tWL must be less than or equal to 1/fSCK.