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ATWINC15x0B-MU IEEE® 802.11 b/g/n Network Controller SoC
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10
Design Consideration
10.2
Sensitive Traces
Introduction
Features
1
Ordering Information and IC Marking
2
Functional Overview
3
Clocking
4
CPU and Memory Subsystem
5
WLAN Subsystem
6
External Interfaces
7
Power Management
8
Electrical Specifications
9
Reference Design
10
Design Consideration
10.1
Placement and Routing Guidelines
10.2
Sensitive Traces
10.2.1
Signals
10.2.2
Supplies
10.3
Interferers
10.4
Antenna
10.5
Reflow Profile Information
11
Package Outline Drawing
12
Reference Documentation
13
Document Revision History
The Microchip Website
Product Change Notification Service
Customer Support
Microchip Devices Code Protection Feature
Legal Notice
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Quality Management System
Worldwide Sales and Service
10.2 Sensitive Traces
This section describes the guidelines for sensitive traces and signals.
