2.1 LVPECL Application

Note: Resistor values as shown in the figure below are typically 140Ω for 3.3V operation and 84Ω for 2.5V operation.

Figure 2-1. Single Resistor Termination Scheme

The VC-708 incorporates a standard PECL output scheme, which are unterminated FET drains. There are numerous application notes on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground in the figure above, and a pull-up/pull-down scheme as shown in the figure below. AC coupling capacitor are optional, depending on the application and the input logic requirements of the next stage.

One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left unterminated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50Ω impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems.

Note: Resistor values shown in the figure below are typical for 3.3V operation. For 2.5V operation, the resistor to ground is 62Ω and the resistor to supply is 250Ω.

Figure 2-2. Pull-Up Pull Down Termination