3.2.1 PIOA Pin Description

Table 3-1. PIOA Pin Description
Pad No. Power Rail I/O Type Primary Alternate PIO Peripheral Reset State (Signal, Dir, PU, PD, HiZ, ST) Note
Signal Dir Signal Dir Func Signal Dir IO Set
165 VDDSDHC GPIO_EMMC PA0 I/O A SDMMC0_CK I/O 1 PIO, I, PU, ST
B QSPI0_SCK O 1
F D0 I/O 2
162 VDDSDHC GPIO_EMMC PA1 I/O A SDMMC0_CMD I/O 1 PIO, I, PU, ST
B QSPI0_CS O 1
F D1 I/O 2
166 VDDSDHC GPIO_EMMC PA2 I/O A SDMMC0_DAT0 I/O 1 PIO, I, PU, ST
B QSPI0_IO0 I/O 1
F D2 I/O 2
164 VDDSDHC GPIO_EMMC PA3 I/O A SDMMC0_DAT1 I/O 1 PIO, I, PU, ST
B QSPI0_IO1 I/O 1
F D3 I/O 2
169 VDDSDHC GPIO_EMMC PA4 I/O A SDMMC0_DAT2 I/O 1 PIO, I, PU, ST
B QSPI0_IO2 I/O 1
F D4 I/O 2
163 VDDSDHC GPIO_EMMC PA5 I/O A SDMMC0_DAT3 I/O 1 PIO, I, PU, ST
B QSPI0_IO3 I/O 1
F D5 I/O 2
171 VDDSDHC GPIO_EMMC PA6 I/O A SDMMC0_DAT4 I/O 1 PIO, I, PU, ST Note (2)
B QSPI1_SCK O 1
D TIOA5 I/O 1
E FLEXCOM2_IO0 I/O 1
F D6 I/O 2
173 VDDSDHC GPIO_EMMC PA7 I/O A SDMMC0_DAT5 I/O 1 PIO, I, PU, ST Note (2)
B QSPI1_IO0 I/O 1
D TIOB5 I/O 1
E FLEXCOM2_IO1 I/O 1
F D7 I/O 2
167 VDDSDHC GPIO_EMMC PA8 I/O A SDMMC0_DAT6 I/O 1 PIO, I, PU, ST Note (2)
B QSPI1_IO1 I/O 1
D TCLK5 I 1
E FLEXCOM2_IO2 I/O 1
F NWE/NANDWE O 2
172 VDDSDHC GPIO_EMMC PA9 I/O A SDMMC0_DAT7 I/O 1 PIO, I, PU, ST Note (2)
B QSPI1_IO2 I/O 1
D TIOA4 I/O 1
E FLEXCOM2_IO3 O 1
F NCS3 O 2
168 VDDSDHC GPIO_EMMC PA10 I/O A SDMMC0_RSTN O 1 PIO, I, PU, ST Note (2)
B QSPI1_IO3 I/O 1
D TIOB4 I/O 1
E FLEXCOM2_IO4 O 1
F A21/NANDALE O 2
174 VDD_3V3 GPIO PA11 I/O A SDMMC0_VDDSEL O 1 PIO, I, PU, ST
B QSPI1_CS O 1
D TCLK4 I 1
F A22/NANDCLE O 2
170 VDD_3V3 GPIO PA12 I/O A SDMMC0_WP I 1 PIO, I, PU, ST
B IRQ I 1
F NRD/NANDOE O 2
175 VDD_3V3 GPIO PA13 I/O A SDMMC0_CD I 1 PIO, I, PU, ST Note (3)
E FLEXCOM3_IO1 I/O 1
21 VDD_3V3 GPIO_QSPI PA14 I/O A SPI0_SPCK I/O 1 PIO, I, PU, ST Note (3)
B TK1 I/O 1
D I2SMCK1 O 2
E FLEXCOM3_IO2 I/O 1
22 VDD_3V3 GPIO PA15 I/O A SPI0_MOSI I/O 1 PIO, I, PU, ST Note (3)
B TF1 I/O 1
D I2SCK1 I/O 2
E FLEXCOM3_IO0 I/O 1
23 VDD_3V3 GPIO_IO PA16 I/O A SPI0_MISO I/O 1 PIO, I, PU, ST Note (3)
B TD1 O 1
D I2SWS1 I/O 2
E FLEXCOM3_IO3 O 1
24 VDD_3V3 GPIO_IO PA17 I/O A SPI0_NPCS0 I/O 1 PIO, I, PU, ST Note (3)
D I2SDI1 I 2
E FLEXCOM3_IO4 O 1
76 VDD_3V3 GPIO PA30 I/O C SPI0_NPCS0 I/O 2 PIO, I, PU, ST Note (3)
D PWMH0 O 1
75 VDD_3V3 GPIO PA31 I/O C SPI0_MISO I/O 2 PIO, I, PU, ST Note (3)
D PWML0 O 1
Note:
  1. Fixed feature due to the WLSOM1 internal connection.
  2. Limited feature compared to SAMA5D2 due to the WLSOM1 internal use of specific functionality, for example, QSPI, GMAC.
  3. Limited feature compared to SAMA5D2 due to the use of a part of the functionality for other features in the WLSOM1, for example, GMAC, ISC, FLEXCOM, etc.