3.2.5 System Pins Description

Table 3-4. System Pins Description
Pin No. Pin Name Power Rail Description
145 CLK_AUDIO VDD_3V3 Audio Main System Bus Clock Frequency Output
151 USBA_N VDD_3V3 USB Device High-Speed Data -
152 USBA_P VDD_3V3 USB Device High-Speed Data +
157 HSIC_STROBE VDDHSIC (1.2V) USB High-Speed Inter-Chip Strobe
156 HSIC_DATA VDDHSIC (1.2V) USB High-Speed Inter-Chip Data
153 USBB_N VDD_3V3 USB Host Port B High-Speed Data -
154 USBB_P VDD_3V3 USB Host Port B High-Speed Data +
7 NRST VDDBU Module Reset

A 100 kOhm pull-up must be provided by the host board
140 COMPN VDDBU External Analog Data Input
139 COMPP VDDBU External Analog Data Input
146 PIOBU1 VDDBU Tamper I/O #1
135 PIOBU2 VDDBU Tamper I/O #2
137 PIOBU3 VDDBU Tamper I/O #3
147 PIOBU4 VDDBU Tamper I/O #4
138 PIOBU5 VDDBU Tamper I/O #5
148 PIOBU6 VDDBU Tamper I/O #6
136 PIOBU7 VDDBU Tamper I/O #7
134 RXD VDDBU RXLP Receive Data Input
10 SHDN VDDBU Shutdown Control
187 WKUP VDDBU Module Wake-Up

A 100 kOhm pull-up to VDDBU must be provided by the host board
178 VTH VDD_MAIN Low Voltage Threshold Detection Input
101 NCS_QSPI VDD_3V3 Embedded QSPI Chip Select Input
83 NC – Not connected
41 NC – Not connected
89 ETH_TX_P – Physical Transmit Signal (+ differential)
88 ETH_TX_N – Physical Transmit Signal (– differential)
87 ETH_RX_P – Physical Receive Signal (+ differential)
86 ETH_RX_N – Physical Receive Signal (– differential)
84 ETH_LED0 VDD_3V3 Programmable LED0 Output
182 nSTART_SOM VDD_MAIN Module Start-Up Control Input
42 RXD_WILC_DBG VDD_3V3 Used for Radio Debug. UART RXD
43 TXD_WILC_DBG VDD_3V3 Used for Radio Debug. UART TXD