4.6.9.2 Design Layout Recommendations

When designing the LCD interface, consider the following recommendations:

Match the LCD signal lengths to within 50 mils. Affected PIOs in the example above are PC10 to PC27, PC30, PC31, PD0 and PD1.
Place the clock line (PD0) at least 3 times the trace width away from other signals for noise immunity.
Place data signals at least 2 times the trace width away from any other data trace.
Design data signals at least 2 times the trace width away from any copper plan.

Figure 4-33. LCD Layout Example