5.1.1 Basic Control

Clause 22 Basic Control Register
Name: BASIC_CONTROL
Address: 0x00

Bit 15141312111098 
 SW_RESETLOOPBACKSPD_SEL[0]AUTONEGENPDISOLATEREAUTONEGDUPLEXMD 
Access R/W SCR/WROROR/WR/WRORO 
Reset 00000000 
Bit 76543210 
 COLTSTSPD_SEL[1] 
Access R/WRORORORORORORO 
Reset 00000000 

Bit 15 – SW_RESET PHY Soft Reset

Writing a ‘1’ to this bit will initiate a software reset of the PHY. A software reset will restore all PHY registers to their default state, except for those fields identified as “NASR”.
Note: This bit is self-clearing. When setting this bit, do not set other bits in this register.
ValueDescription
0 Normal operation
1 PHY software reset

Bit 14 – LOOPBACK Near-End Loopback

When set, this bit enables a near-end loopback. When enabled, transmit data (TXD) pins from the MAC will be looped back onto the receive data (RXD) pins to the MAC. In this mode, no signal is transmitted onto the network media.

Important: PLCA must be disabled or configured as the PLCA Coordinator (Local ID = 0) when the near-end loopback mode is enabled.
ValueDescription
0 Normal operation
1 Enable near-end loopback mode

Bit 13 – SPD_SEL[0] PHY Speed Select

Together with SPD_SEL[1], sets the network communication speed.
Note: Only 10 Mbit/s is supported. This bit is always ‘0’.
ValueDescription
00 10 Mbit/s
01 100 Mbit/s
10 1000 Mbit/s
11 Reserved

Bit 12 – AUTONEGEN Auto-Negotiation Enable

Note: Auto-negotiation is not supported. This bit is always ‘0’.
ValueDescription
0 Disable auto-negotiate process
1 Enable auto-negotiate process

Bit 11 – PD Power Down

Setting this bit will power down the PMA leaving the remainder of the device functional.
Note: This bit is the same as the Low Power Enable bit in the 10BASE-T1S PMA Control register.
ValueDescription
0 Normal operation
1 PMA is powered down

Bit 10 – ISOLATE Electrical isolation of the PHY from MII/RMII

When this bit is set, the PHY will electrically isolate its data paths from the MII/RMII .
ValueDescription
0 Normal operation (PHY is not electrically isolated from MII/RMII )
1 Electrical isolation of PHY from MII/RMII

Bit 9 – REAUTONEG Restart Auto-Negotiation

Note: Auto-negotiation is not supported. This bit is always ‘0’.
ValueDescription
0 Normal operation
1 Restart auto-negotiate process

Bit 8 – DUPLEXMD Duplex Mode

This bit configures the PHY for full-duplex or half-duplex network communication.
Note: Only half duplex operation is supported. This bit is always ‘0’.
ValueDescription
0 Half duplex
1 Full duplex

Bit 7 – COLTST Collision Test

When the Near-End Loopback is enabled (LOOPBACK), setting this bit will allow the COL pin to be tested. When the Collision Test is enabled, asserting TXEN will cause the COL output to go high within 512 bit times. Negating TXEN will cause the COL output to go low within 4 bit times. The Collision Test should only be enabled when Near-End Loopback is enabled.
ValueDescription
0 Normal operation. Collision test is disabled.
1 Enable collision test

Bit 6 – SPD_SEL[1] PHY Speed Select

See description for SPD_SEL[0] for details.
Note: Only 10 Mbit/s operation is supported. This bit is always ‘0’.