4.1.1 Single Clock Media Independent Interface (SC-MII)
The Single Clock Media Independent Interface (SC-MII) provides a common interface between physical layer and MAC layer devices similar to the MII but with fewer pins while maintaining compatibility with the MII. The Single Clock MII combines the Transmit Clock (TXCLK) and Receive Clock (RXCLK) into a Single Media Clock (SMCLK) and does not include the Transmit Error (TXER) pin. The result is a reduction of two pins over the standard MII which may be used for additional features.
The Single Clock MII includes the following interface signals:
- Transmit Data - TXD[3:0]
- Transmit Enable - TXEN
- Receive Data - RXD[3:0]
- Receive Data Valid - RXDV
- Receive Error - RXER
- Single Media Clock - SMCLK
- Carrier Sense - CRS
- Collision Detect - COL
In Single Clock MII mode, the LAN8670 drives the Single Media Clock (SMCLK) to both the controller TXCLK and RXCLK input pins. On the transmit path, the controller synchronizes the transmit data to the rising edge of the SMCLK as received at its TXCLK input. The controller drives TXEN high to indicate valid transmit data on TXD[3:0]. The device will synchronously capture TXEN and TXD[3:0] on the falling edge of TXCLK. Support for TXER is not provided in Single Clock MII mode.
On the Single Clock MII receive path, the device drives receive data, RXD[3:0], synchronously to the Single Media Clock (SMCLK). When the device drives RXDV high, the controller captures in the receive data on the rising edge of SMCLK as received at its RXCLK input. The device drives RXER high when a receive error is detected (e.g., an uncorrectable decoding error). The device synchronizes RXD[3:0], RXDV, and RXER to change on the falling edge of SMCLK.
The CRS and COL signals are asserted asynchronously to the clocks.