10.2.2 SPI Timing

The SPI Slave interface supports four standard modes as determined by the Clock Polarity (CPOL) and Clock Phase (CPHA) settings. These modes are illustrated in the following table and figure.

Table 10-3. SPI Slave Modes
Mode	CPOL	CPHA
0	0	0
1	0	1
2	1	0
3	1	1

Note: The ATWINC3400-MR210xA firmware uses SPI MODE 0 to communicate with the host.

The red lines in the following figure correspond to Clock Phase = 0 and the blue lines correspond to Clock Phase = 1.

Figure 10-2. SPI Slave Clock Polarity and Clock Phase Timing

The SPI timing is provided in the following figure and table.

Figure 10-3. SPI Timing Diagram (SPI Mode CPOL = 0, CPHA = 0)

Table 10-4. SPI Slave Timing Parameters⁽
Parameter	Symbol	Min.	Max.	Units
Clock Input Frequency⁽²⁾	f_SCK	—	48	MHz
Clock Low Pulse Width	t_WL	4	—	ns
Clock High Pulse Width	t_WH	5	—
Clock Rise Time	t_LH	0	7
Clock Fall Time	t_HL	0	7
TXD Output Delay⁽³⁾	t_ODLY	4	9 from SCK fall
RXD Input Setup Time	t_ISU	1	—
RXD Input Hold Time	t_IHD	5	—
SSN Input Setup Time	t_SUSSN	3	—
SSN Input Hold Time	t_HDSSN	5.5	—

Note:

The timing is applicable to all SPI modes.
The maximum clock frequency specified is limited by the SPI Slave interface internal design; the actual maximum clock frequency can be lower and depends on the specific PCB layout.
The timing is based on 15 pF output loading. Under all conditions, t_LH + t_WH + t_HL + t_WL must be less than or equal to 1/ f_SCK.