12.10.3 PIE1
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt controlled by registers PIE1 through
PIE7.
| Name: | PIE1 |
| Offset: | 0x0097 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TMR1GIE | TMR1IE | OSFIE | CSWIE | ACTIE | SCANIE | CRCIE | NVMIE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – TMR1GIE TMR1 Gate Interrupt Enable
| Value | Description |
|---|---|
| 1 | TMR1 Gate interrupts are enabled |
| 0 | TMR1 Gate interrupts are disabled |
Bit 6 – TMR1IE TMR1 Interrupt Enable
| Value | Description |
|---|---|
| 1 | TMR1 interrupts are enabled |
| 0 | TMR1 interrupts are disabled |
Bit 5 – OSFIE Oscillator Failure Interrupt Enable
| Value | Description |
|---|---|
| 1 | Oscillator Failure interrupts are enabled |
| 0 | Oscillator Failure interrupts are disabled |
Bit 4 – CSWIE Clock Switch Interrupt Enable
| Value | Description |
|---|---|
| 1 | Clock Switch interrupts are enabled |
| 0 | Clock Switch interrupts are disabled |
Bit 3 – ACTIE Active Clock Tuning Interrupt Enable
| Value | Description |
|---|---|
| 1 | Active Clock Tuning interrupts are enabled |
| 0 | Active Clock Tuning interrupts are disabled |
Bit 2 – SCANIE Memory Scanner Interrupt Enable
| Value | Description |
|---|---|
| 1 | Memory Scanner interrupts are enabled |
| 0 | Memory Scanner interrupts are disabled |
Bit 1 – CRCIE CRC Interrupt Enable
| Value | Description |
|---|---|
| 1 | CRC interrupts are enabled |
| 0 | CRC interrupts are disabled |
Bit 0 – NVMIE NVM Interrupt Enable
| Value | Description |
|---|---|
| 1 | NVM interrupts are enabled |
| 0 | NVM interrupts are disabled |