26.5.3 Master Control A

Name: MCTRLA
Offset: 0x03
Reset: 0x00
Property: -

Bit 76543210 
 RIENWIEN QCENTIMEOUT[1:0]SMENENABLE 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – RIEN Read Interrupt Enable

A TWI master read interrupt will be generated only if this bit and the Global Interrupt Enable (I) bit in the Status (CPU.SREG) register are set to ‘1’.

Writing a ‘1’ to this bit enables the interrupt on the Read Interrupt Flag (RIF) in the Master Status (TWIn.MSTATUS) register. When the master read interrupt occurs, the RIF flag is set to ‘1’.

Bit 6 – WIEN Write Interrupt Enable

A TWI master write interrupt will be generated only if this bit and the Global Interrupt Enable (I) bit in the Status (CPU.SREG) register are set to ‘1’.

Writing a ‘1’ to this bit enables the interrupt on the Write Interrupt Flag (WIF) in the Master Status (TWIn.MSTATUS) register. When the master write interrupt occurs, the WIF flag is set to ‘1’.

Bit 4 – QCEN Quick Command Enable

Writing a ‘1’ to this bit enables the Quick Command mode. If the Quick Command mode is enabled and a slave acknowledges the address, the corresponding Read Interrupt Flag (RIF) or Write Interrupt Flag (WIF) will be set depending on the value of R/W bit.

The software must issue a Stop command by writing to the Command (MCMD) bit field in the Master Control B (TWIn.MCTRLB) register.

Bits 3:2 – TIMEOUT[1:0] Inactive Bus Time-Out

Setting this bit field to a nonzero value will enable the inactive bus time-out supervisor. If the bus is inactive for longer than the TIMEOUT setting, the bus state logic will enter the Idle state.

ValueNameDescription
0x0 DISABLED Bus time-out disabled - I2C
0x1 50US 50 µs - SMBus (assume the baud rate is set to 100 kHz)
0x2 100US 100 µs (assume the baud rate is set to 100 kHz)
0x3 200US 200 µs (assume the baud rate is set to 100 kHz)

Bit 1 – SMEN Smart Mode Enable

Writing a ‘1’ to this bit enables the Master Smart mode. When the Smart mode is enabled, the existing value in the Acknowledge Action (ACKACT) bit from the Master Control B (TWIn.MCTRLB) register is sent immediately after reading the Master Data (TWIn.MDATA) register.

Bit 0 – ENABLE Enable TWI Master

Writing a ‘1’ to this bit enables the TWI as master.