26.5.7 Master Address

Name: MADDR
Offset: 0x07
Reset: 0x00
Property: -

Bit 76543210 
 ADDR[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7:0 – ADDR[7:0] Address

This register contains the address of the external slave device. When this bit field is written, the TWI will issue a Start condition, and the shift register performs a byte transmit operation on the bus depending on the bus state.

This register can be read at any time without interfering with the ongoing bus activity since a read access does not trigger the master logic to perform any bus protocol related operations.

The master control logic uses the bit 0 of this register as the R/W direction bit.