26.5.4 Master Control B

Name: MCTRLB
Offset: 0x04
Reset: 0x00
Property: -

Bit 76543210 
     FLUSHACKACTMCMD[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 3 – FLUSH Flush

This bit clears the internal state of the master and the bus states changes to Idle. The TWI will transmit invalid data if the Master Data (TWIn.MDATA) register is written before the Master Address (TWIn.MADDR) register.

Writing a ‘1’ to this bit generates a strobe for one clock cycle, disabling the master, and then re-enabling the master. Writing a ‘0’ to this bit has no effect.

Bit 2 – ACKACT Acknowledge Action

The ACKACT(1) bit represents the behavior in the Master mode under certain conditions defined by the bus state and the software interaction. If the Smart Mode Enable (SMEN) bit in the Master Control A (TWIn.MCTRLA) register is set to ‘1’, the acknowledge action is performed when the Master Data (TWIn.MDATA) register is read, else a command must be written to the Command (MCDM) bit field in the Master Control B (TWIn.MCTRLB) register.

The acknowledge action is not performed when the Master Data (TWIn.MDATA) register is written, since the master is sending data.

ValueNameDescription
0 ACK Send ACK
1 NACK Send NACK

Bits 1:0 – MCMD[1:0] Command

The MCMD(1) bit field is a strobe. This bit field is always read as ‘0’.

Writing to this bit field triggers a master operation as defined by the table below.

Table 26-2. Command Settings
MCMD[1:0] Group Configuration DIR Description
0x0 NOACT X Reserved
0x1 REPSTART X Execute Acknowledge Action followed by repeated Start condition
0x2 RECVTRANS W

Execute Acknowledge Action (no action) followed by a byte write operation(2)
R Execute Acknowledge Action followed by a byte read operation
0x3 STOP X Execute Acknowledge Action followed by issuing a Stop condition
Note:
  1. The ACKACT bit and the MCMD bit field can be written at the same time.
  2. For a master write operation, the TWI will wait for new data to be written to the Master Data (TWIn.MDATA) register.