26.5.11 Slave Status


Bit	7	6	5	4	3	2	1	0
	DIF	APIF	CLKHOLD	RXACK	COLL	BUSERR	DIR	AP
Access	R/W	R/W	R	R	R/W	R/W	R	R
Reset	0	0	0	0	0	0	0	0

Bit 7 – DIF Data Interrupt Flag

This flag is set to ‘1’ when the slave byte transmit or receive operation is completed without any bus errors. This flag can be set to ‘1’ with an unsuccessful transaction in case of collision detection. More information can be found in the Collision (COLL) bit description.

The DIF flag can generate a slave data interrupt. More information can be found in Data Interrupt Enable (DIEN) bit from the Slave Control A (TWIn.SCTRLA) register.

This flag is automatically cleared when accessing several other TWI registers. The DIF flag can be cleared by choosing one of the following methods:

Writing/Reading the Slave Data (TWIn.SDATA) register.
Writing to the Command (SCMD) bit field from the Slave Control B (TWIn.SCTRLB) register.

Bit 6 – APIF Address or Stop Interrupt Flag

This flag is set to ‘1’ when the slave address has been received or by a Stop condition.

The APIF flag can generate a slave address or stop interrupt. More information can be found in the Address or Stop Interrupt Enable (APIEN) bit from the Slave Control A (TWIn.SCTRLA) register.

This flag can be cleared by choosing one of the methods described for the DIF flag.

Bit 5 – CLKHOLD Clock Hold

When this bit is read as ‘1’, it indicates that the slave is currently holding the SCL low, stretching the TWI clock period.

This bit is set to ‘1’ when an address or data interrupt occurs. Resetting the corresponding interrupt will indirectly set this bit to ‘0’.

Bit 4 – RXACK Received Acknowledge

When this flag is read as ‘0’, it indicates that the most recent Acknowledge bit from the master was ACK.

When this flag is read as ‘1’, it indicates that the most recent Acknowledge bit from the master was NACK.

Bit 3 – COLL Collision

When this bit is read as ‘1’, it indicates that the slave has not been able to do one of the following:

Transmit high bits on the SDA. The Data Interrupt Flag (DIF) will be set to ‘1’ at the end as a result of the internal completion of an unsuccessful transaction.
Transmit the NACK bit. The collision occurs because the slave address match already took place, and the APIF flag is set to ‘1’ as a result.

Writing a ‘1’ to this bit will clear the COLL flag. The flag is automatically cleared if any Start condition (S/Sr) is detected.

Note: The APIF and DIF flags can only generate interrupts whose handlers can be used to check for the collision.

Bit 2 – BUSERR Bus Error

The BUSERR flag indicates that an illegal bus operation has occurred. Illegal bus operation is detected if a protocol violating the Start (S), repeated Start (Sr), or Stop (P) conditions are detected on the TWI bus lines. A Start condition directly followed by a Stop condition is one example of a protocol violation.

Writing a ‘1’ to this bit will clear the BUSERR flag.

The TWI bus error detector is part of the TWI Master circuitry. For the bus errors to be detected by the slave, the TWI Master must be enabled, and the main clock frequency must be at least four times the SCL frequency. The TWI Master can be enabled by writing a ‘1’ to the ENABLE bit in the TWIn.MCTRLA register.

Bit 1 – DIR Read/Write Direction

This bit indicates the current TWI bus direction. The DIR bit reflects the direction bit value from the last address packet received from a master TWI device.

When this bit is read as ‘1’, it indicates that a master read operation is in progress.

When this bit is read as ‘0’, it indicates that a master write operation is in progress.

Bit 0 – AP Address or Stop

When the TWI slave Address or Stop Interrupt Flag (APIF) is set to ‘1’, this bit determines whether the interrupt is due to an address detection or a Stop condition.