26.5.8 Master Data
| Name: | MDATA |
| Offset: | 0x08 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – DATA[7:0] Data
This bit field provides direct access to the master’s physical shift register, which is used to shift out data on the bus (transmit) and to shift in data received from the bus (receive). The direct access implies that the MDATA register cannot be accessed during byte transmissions.
Reading valid data or writing data to be transmitted can only be
successful when the CLKHOLD bit is read as ‘1’ or when an
interrupt occurs.
A write access to the MDATA register will command the master to
perform a byte transmit operation on the bus, directly followed by receiving the
Acknowledge bit from the slave. This is independent of the Acknowledge Action
(ACKACT) bit from the Master Control B (TWIn.MCTRLB) register. The write
operation is performed regardless of winning or losing arbitration before the
Write Interrupt Flag (WIF) is set to ‘1’.
If the Smart Mode Enable (SMEN) bit in the Master Control A
(TWIn.MCTRLA) register is set to ‘1’, a read access to the
MDATA register will command the master to perform an acknowledge action. This is
dependent on the setting of the Acknowledge Action (ACKACT) bit from the Master
Control B (TWIn.MCTRLB) register.
- The WIF and RIF interrupt flags are cleared automatically if the MDATA
register is read while ACKACT is set to ‘
1’. - The ARBLOST and BUSEER flags are left unchanged.
- The WIF, RIF, ARBLOST, and BUSERR flags together with the Clock Hold (CLKHOLD) bit are all located in the Master Status (TWIn.MSTATUS) register.