3.1 Features

Key features of the Math block are as follows:
  • High-performance and power optimized multiplication operations.
  • Full-precision 48-bit output width.
  • Supports 18 x 19 signed multiplication.
  • Supports 17 x 18 unsigned multiplications.
  • Supports input and output pipeline registers.
  • Supports Dot-Product (DOTP) mode.
  • Supports Single-Instruction Multiple-Data (SIMD) mode (Dual-Independent mode).
  • Internal pre-adder block enables the efficient implementation of symmetric filters.
  • Supports input cascade chain to form the tap-delay line for filtering applications.
  • Built-in addition, subtraction, and accumulation units to combine multiplication results efficiently.
  • Independent 48-bit registered third input.
  • Supports signed and unsigned operations.
  • Internal cascade signals (48-bit CDIN and CDOUT) enable cascading of the Math blocks.