3.3 Functional Description

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Math blocks are arranged in rows in the FPGA fabric and can be cascaded in a chain, starting from the left-most block to the right-most block within a row.

Each Math block consists of:

The following figure shows the simplified block diagram of the Math block.

Figure 3-1. Simplified Functional Block Diagram of Math Block

The following table lists the ports of the Math block.

Table 3-1. Port List for Math Block
Port Name	Direction	Type	Polarity	Description
A[17:0]	Input	Dynamic	Active high	Input data for operand A when USE_ROM = 0
ARSHFT17	Input	Dynamic	Active high	Arithmetic right-shift for operand E. When asserted, a 17-bit arithmetic right-shift is performed on operand E
B[17:0]	Input	Dynamic	Active high	Input data B to pre-adder with data D
B2[17:0]	Output	Dynamic	Active high	Pipelined output of input data B. Result P must be floating when B2 is used.
BCOUT[17:0]	Output	Cascade	Active high	Cascade output of B2. Value of BCOUT is the same as B2. The entire bus must either be dangling or drive an entire B input of another MACC_PA or MACC_PA_BC_ROM block.
C[47:0]	Input	Dynamic	Active high	Input data C When DOTP = 1, connect C[8:0] to CARRYIN. When SIMD = 1, connect C[8:0] to 0.
CLK	Input	Dynamic	Rising edge	Clock for A, B, C, CARRYIN, D, P, OVFL_CARRYOUT, ARSHFT17, CDIN_FDBK_SEL, PASUB, and SUB registers
CARRYIN	Input	Dynamic	Active high	CARRYIN for input data C
CDIN[47:0]	Input	Cascade	Active high	Cascaded input for operand E The entire bus must be driven by an entire CDOUT of another Math block. In Dot-product mode, the driving CDOUT must also be generated by a Math block in Dot-product mode.
CDIN_FDBK_SEL[1:0]	Input	Dynamic	Active high	Select CDIN, P, or 0 for operand E
CDOUT[47:0]	Output	Cascade	Active high	Cascade output of result P Value of CDOUT is the same as P. The entire bus must either be dangling or drive an entire CDIN of another Math block in cascaded mode.
D[17:0]	Input	Dynamic	Active high	Input data D to pre-adder with data B When SIMD = 1, connect D[8:0] to 0.
OVFL_CARRYOUT	Output	—	Active high	OVERFLOW or CARRYOUT
P[47:0]	Output	—	Active high	Result data
PASUB	Input	Dynamic	Active high	Subtract operation for pre-adder of B and D
ROM_ADDR[3:0]	Input	Dynamic	Active high	Address of ROM data for operand A when USE_ROM = 1
SUB	Input	Dynamic	Active high	Subtract operation

Note: For information about asynchronous reset, synchronous reset, bypass, and enable signal details for each input/output register, see Table 5-17.