34.8.4 Interrupt Enable Clear
Name: | INTENCLR |
Offset: | 0x14 |
Reset: | 0x00 |
Property: | PAC Write-Protection |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ERROR | RXFF | TXFE | DRDY | AMATCH | PREC | ||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ERROR Error Interrupt Enable
Writing ‘0
’ to this bit has no effect.
Writing ‘1
’ to this bit clears the Error Interrupt Enable
bit, which disables the Error interrupt.
Value | Description |
---|---|
0 | Error interrupt is disabled. |
1 | Error interrupt is enabled. |
Bit 4 – RXFF RX FIFO Full Interrupt Enable
Writing ‘0
’ to this bit has no effect.
Writing ‘1
’ to this bit clears the RX FIFO Full bit, which disables
the RX FIFO Full interrupt.
Value | Description |
---|---|
0 | The RX FIFO Full interrupt is disabled. |
1 | The RX FIFO Full interrupt is enabled. |
Bit 3 – TXFE TX FIFO Empty Interrupt Enable
Writing ‘0
’ to this bit has no effect.
Writing ‘1
’ to this bit clears the TX FIFO Empty bit, which disables
the TX FIFO Empty interrupt.
Value | Description |
---|---|
0 | The TX FIFO Empty interrupt is disabled. |
1 | The TX FIFO Empty interrupt is enabled. |
Bit 2 – DRDY Data Ready Interrupt Enable
Writing ‘0
’ to this bit has no effect.
Writing ‘1
’ to this bit clears the Data Ready bit, which
disables the Data Ready interrupt.
Value | Description |
---|---|
0 | The Data Ready interrupt is disabled. |
1 | The Data Ready interrupt is enabled. |
Bit 1 – AMATCH Address Match Interrupt Enable
Writing ‘0
’ to this bit has no effect.
Writing ‘1
’ to this bit clears the Address Match Interrupt
Enable bit, which disables the Address Match interrupt.
Value | Description |
---|---|
0 | The Address Match interrupt is disabled. |
1 | The Address Match interrupt is enabled. |
Bit 0 – PREC Stop Received Interrupt Enable
Writing ‘0
’ to this bit has no effect.
Writing ‘1
’ to this bit clears the Stop Received Interrupt
Enable bit, which disables the Stop Received interrupt.
Value | Description |
---|---|
0 | The Stop Received interrupt is disabled. |
1 | The Stop Received interrupt is enabled. |