34.8.6 Interrupt Flag Status and Clear

This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. The corresponding bits in STATUS are LENERR, SEXTTOUT, LOWTOUT, COLL and BUSERR.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit will clear the flag.

This flag is set when RX FIFO Threshold locations are fulfilled.

The flag is cleared when the RX FIFO is empty.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit will clear the RX FIFO Full interrupt flag.

This flag is set when TX FIFO Threshold locations are available.

The flag is cleared when the TX FIFO is full.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit will clear the TX FIFO Empty interrupt flag.

This flag is set when a I²C client byte transmission is successfully completed.

The flag is cleared by hardware when either:

• Writing to the DATA register.
• Reading the DATA register with Smart mode enabled.
• Writing a valid command to the CMD register.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit will clear the Data Ready Interrupt flag.

This flag is set when the I²C client address match logic detects that a valid address has been received.

The flag is cleared by hardware when CTRL.CMD is written.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit will clear the Address Match Interrupt flag. When cleared, an ACK/NACK will be sent according to CTRLB.ACKACT.

This flag is set when a Stop condition is detected for a transaction being processed. A Stop condition detected between a bus host and another client will not set this flag, unless the PMBus Group Command is enabled in the Control B register (CTRLB.GCMD=1).

This flag is cleared by hardware after a command is issued on the next address match.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit will clear the Stop Received Interrupt flag.