17.4.2.1.2 Master Clear Reset (EXTR)

Whenever the master clear pin (MCLR) is driven low, the Reset event is synchronized with the system clock, SYS_CLK, before asserting the SYSRST, provided the input pulse on MCLR is longer than a certain minimum width, as specified in the Electrical Specifications.

The MCLR pin provides a filter to minimize the effects of noise and to avoid unwanted Reset events. The RCON.EXTR status bit is set to indicate the MCLR Reset.

EXTR is not a true POR. The user can configure the MCLR pin to generate a POR event by configuring the CFGCON1.SMCLR bit rather than an EXTR event.