33.8.2 Control B


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	FIFOCLR[1:0]						RXEN
Access	R/W	R/W					R/W
Reset	0	0					0


Bit	15	14	13	12	11	10	9	8
	AMODE[1:0]		MSSEN				SSDE
Access	R/W	R/W	R/W				R/W
Reset	0	0	0				0


Bit	7	6	5	4	3	2	1	0
		PLOADEN				CHSIZE[2:0]
Access		R/W				R/W	R/W	R/W
Reset		0				0	0	0

Bits 23:22 – FIFOCLR[1:0] FIFO Clear

When these bits are set, the corresponding FIFO is cleared. The bits automatically clears when SYNCBUSY.CTRLB = 0.

These bits are not enable-protected.


FIFOCLR[1:0]	Name	Description
0x0	NONE	No action
0x1	TXFIFO	Clear TX FIFO
0x2	RXFIFO	Clear RX FIFO
0x3	BOTH	Clear both TX/RX FIFO

Bit 17 – RXEN Receiver Enable

Writing ‘0’ to this bit disables the SPI receiver immediately. The receive buffer is flushed, data from ongoing receptions are lost and STATUS.BUFOVF is cleared.

Writing ‘1’ to CTRLB.RXEN when the SPI is disabled sets CTRLB.RXEN immediately. When the SPI is enabled, CTRLB.RXEN is cleared, SYNCBUSY.CTRLB is set and remains set until the receiver is enabled. When the receiver is enabled, CTRLB.RXEN reads back as ‘1’.

Writing ‘1’ to CTRLB.RXEN when the SPI is enabled sets SYNCBUSY.CTRLB, which remains set until the receiver is enabled, and CTRLB.RXEN reads back as ‘1’.

This bit is not enable-protected.

Value	Description
0	The receiver is disabled.
1	The receiver is enabled or it is enabled when SPI is enabled.

Bits 15:14 – AMODE[1:0] Address Mode

These bits set the Client Addressing mode when the frame format (CTRLA.FORM) with address is used. They are unused in Host mode.

These bits are not synchronized.


AMODE[1:0]	Name	Description
0x0	MASK	ADDRMASK is used as a mask to the ADDR register
0x1	2_ADDRS	The client responds to the two unique addresses in ADDR and ADDRMASK
0x2	RANGE	The client responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit
0x3	—	Reserved

Bit 13 – MSSEN Host SPI Select Enable

This bit enables hardware SPI Select (SS) control.

This bit is not synchronized.

Value	Description
0	Hardware SS control is disabled.
1	Hardware SS control is enabled.

Bit 9 – SSDE SPI Select Low Detect Enable

This bit enables wake-up when the SPI Select (SS) pin transitions from high-to-low.

This bit is not synchronized.

Value	Description
0	SS low detector is disabled.
1	SS low detector is enabled.

Bit 6 – PLOADEN Client Data Preload Enable

Setting this bit enables preloading of the Client Shift register when there is no transfer in progress. If the SS line is high when DATA is written, it is transferred immediately to the Shift register.

This bit is not synchronized.

Bits 2:0 – CHSIZE[2:0] Character Size

These bits are not synchronized.


CHSIZE[2:0]	Name	Description
0x0	8BIT	8 bits
0x1	9BIT	9 bits
0x2-0x7	—	Reserved

Name:	CTRLB
Offset:	0x04
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-Protected, Write-Synchronized