6.14.1 Peripheral Pin Select Input Register
Note:
- For offset address, see Peripheral Pin Select Input Registers table in the Peripheral Pin Select (PPS) Input Mapping Register Summary from Related Links.
- The user can only change the register values if the IOLOCK configuration bit (CFGCON0.IOLOCK) =
0.
| Name: | [pin name]R |
| Offset: | See the following Note |
| Reset: | 0x00 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| [pin name]R[3:0] | |||||||||
| Access | R/W-0 | R/W-0 | R/W-0 | R/W-0 | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 3:0 – [pin name]R[3:0] Peripheral Pin Select Input bits
Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Input Pin Selection Group 1, Input Pin Selection Group 2, Input Pin Selection Group 3, Input Pin Selection Group 4 and Input Pin Selection Group 5 tables in the Input Mapping in PIC32CX-BZ3 Family of Devices for input pin selection values from Related Links.
Note: This field is only writable when CFGCON0.IOLOCK =
0.