40.8.7 Interrupt Flag Status and Clear

This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value. This flag is set on the next CLK_TC_CNT cycle, and will generate an interrupt request if the corresponding Match or Capture Channel x Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCx) is ‘1’.

Writing a ‘0’ to these bits has no effect.

Writing a ‘1’ to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag

In capture operation, this flag is automatically cleared when CCx register is read.

This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel x interrupt flag is set, in which case there is no place to store the new capture.

Writing a ‘0’ to these bits has no effect.

Writing a ‘1’ to this bit clears the Error interrupt flag.

This flag is set on the next CLK_TC_CNT cycle after an overflow condition occurs, and will generate an interrupt request if INTENCLR.OVF or INTENSET.OVF is ‘1’.

Writing a ‘0’ to these bits has no effect.

Writing a ‘1’ to this bit clears the Overflow interrupt flag.