40.8.3 Control B Set
Name: | CTRLBSET |
Offset: | 0x05 |
Reset: | 0x00 |
Property: | PAC Write-Protection, Read-synchronized, Write-Synchronized |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CMD[2:0] | ONESHOT | LUPD | DIR | ||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 7:5 – CMD[2:0] Command
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command is executed, the CMD bit group is read back as ‘0
’.
Writing ‘0x0
’ to these bits has no effect.
Writing a value different from ‘0x0
’ to these bits issues a command for execution.
Value | Name | Description |
---|---|---|
0x0 | NONE | No action |
0x1 | RETRIGGER | Force a start, restart or retrigger |
0x2 | STOP | Force a stop |
0x3 | UPDATE | Force update of double buffered registers |
0x4 | READSYNC | Force a read synchronization of COUNT |
Bit 2 – ONESHOT One-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a ‘0
’ to this bit has no effect.
Writing a ‘1
’ to this bit enables one-shot operation.
Value | Description |
---|---|
0 | The TC wraps around and continue counting on an overflow/underflow condition. |
1 | The TC wraps around and stop on the next underflow/overflow condition. |
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TC buffered registers.
When CTRLB.LUPD is set, no update of the registers with a value of its buffered register is performed on the hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before a hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
Writing a ‘0
’ to this bit has no effect.
Writing a ‘1
’ to this bit sets the LUPD bit.
This bit has no effect when input capture operation is enabled.
Value | Description |
---|---|
0 | The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware update condition. |
1 | The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on hardware update condition. |
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a ‘0
’ to this bit has no effect.
Writing a ‘1
’ to this bit sets the bit and make the counter count down.
Value | Description |
---|---|
0 | The timer/counter is counting up (incrementing). |
1 | The timer/counter is counting down (decrementing). |