40.8.5 Interrupt Enable Clear
Name: | INTENCLR |
Offset: | 0x08 |
Reset: | 0x00 |
Property: | PAC Write-Protection |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
MC1 | MC0 | ERR | OVF | ||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bits 4, 5 – MCx Match or Capture Channel x Interrupt Enable [x = 1..0]
Writing a ‘0
’ to these bits has no effect.
Writing a ‘1
’ to MCx will clear the corresponding Match or Capture
Channel x Interrupt Enable bit, which disables the Match or Capture Channel x
interrupt.
Value | Description |
---|---|
0 | The Match or Capture Channel x interrupt is disabled. |
1 | The Match or Capture Channel x interrupt is enabled. |
Bit 1 – ERR Error Interrupt Disable
Writing a ‘0
’ to these bits has no effect.
Writing a ‘1
’ to this bit will clear the Error Interrupt
Enable bit, which disables the Error interrupt.
Value | Description |
---|---|
0 | The Error interrupt is disabled. |
1 | The Error interrupt is enabled. |
Bit 0 – OVF Overflow Interrupt Disable
Writing a ‘0
’ to these bits has no effect.
Writing a ‘1
’ to this bit will clear the Overflow
Interrupt Enable bit, which disables the Overflow interrupt request.
Value | Description |
---|---|
0 | The Overflow interrupt is disabled. |
1 | The Overflow interrupt is enabled. |