40.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the TC is disabled (CTRLA.ENABLE = 0):
- Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits
- Drive Control register (DRVCTRL)
- Wave register (WAVE)
- Event Control register (EVCTRL)
Writing to enable-protected bits and setting the CTRLA.ENABLE bit can be performed in a single 32-bit access of the CTRLA register. Writing to enable-protected bits and clearing the CTRLA.ENABLE bit cannot be performed in a single 32-bit access.
Before enabling the TC, the peripheral must
be configured by the following steps:
- Enable the TC bus clock if not already enabled by default (PB1_CLK).
- Select 8-, 16- or 32-bit counter mode via the TC Mode bit group in the Control A register (CTRLA.MODE). The default mode is 16-bit.
- Select one wave generation operation in the Waveform Generation Operation bit group in the WAVE register (WAVE.WAVEGEN).
- If desired, the GCLK_TCx clock can be prescaled via the Prescaler bit group in the Control A
register (CTRLA.PRESCALER).
- If the prescaler is used, select a prescaler synchronization operation via the Prescaler and Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC).
- If desired, select one-shot operation
by writing a ‘
1
’ to the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT). - If desired, configure the counting
direction down (starting from the TOP value) by writing a ‘
1
’ to the Counter Direction bit in the Control B register (CTRLBSET.DIR). - For capture operation, enable the individual channels to capture in the Capture Channel x Enable bit group in the Control A register (CTRLA.CAPTEN).
- If desired, enable inversion of the waveform output or I/O pin input signal for individual channels via the Invert Enable bit group in the Drive Control register (DRVCTRL.INVEN).