40.6.2.7 Double Buffering
The Compare Channels (CCx) registers, and the Period (PER) register in 8-bit mode are
double buffered. Each buffer register has a buffer valid bit (CCBUFVx or PERBUFV) in the
STATUS register, which indicates that the buffer register contains a new valid value that
can be copied into the corresponding register. As long as the respective buffer valid
status flag (PERBUFV or CCBUFVx) are set to ‘1
’, related syncbusy bits are
set (SYNCBUSY.PER or SYNCBUSY.CCx), a write to the respective PER/PERBUF or CCx/CCBUFx
registers will generate a PAC error, and access to the respective PER or CCx register is
invalid.
1
’ and the Lock
Update bit in the CTRLB register is set to ‘0
’, (writing CTRLBCLR.LUPD to
‘1
’), double buffering is enabled: the data from buffer registers will
be copied into the corresponding register under hardware UPDATE conditions, then the buffer
valid flags bit in the STATUS register are automatically cleared by hardware.Both the registers (PER/CCx) and corresponding buffer registers (PERBUF/CCBUFx) are
available in the I/O register map, and the double buffering feature is not mandatory. The
double buffering is disabled by writing a ‘1
’ to CTRLBSET.LUPD.
1
), when double buffering is enabled
(CTRLBCLR.LUPD=1
), PERBUF register is continuously copied into the PER
independently of update conditions.Changing the Period
The counter period can be changed by writing a new TOP value to the Period register (PER or CC0, depending on the waveform generation mode), which is available in 8-bit mode. Any period update on registers (PER or CCx) is effective after the synchronization delay.
A counter wraparound can occur in any operation mode when up-counting without buffering (see the following figure).
COUNT and TOP are continuously compared, so when a new TOP value that is lower than current COUNT is written to TOP, COUNT will wrap before a compare match.
When double buffering is used, the buffer can be written at any time and the counter will still maintain correct operation. The period register is always updated on the update condition, as shown in the following figure. This prevents wraparound and the generation of odd waveforms.