7.2 VDD Voltage Domain Overview

The PIC32CX-BZ3 Power System VDD Integration Block (SIB) consists of the following modules:
  • Power-on Reset (POR) – Use this module to hold all the components in their inactive state until VDD reaches a stable operating voltage. Use this module to ensure that the supply voltage is sufficient for proper operation of all other analog modules (PD_AVDD) in the Power SIB module.
  • Bandgap (BG) – This module provides a stable reference voltage for Brown-out Reset, ADC, Flash, Comparators and low-voltage detect. The ADC, Flash and Comparators are outside the Power SIB module.
  • Single core voltage regulator (CLDO)-based architecture is used in the RF-Analog section.
  • Feed the voltage regulator (CLDO) with 1.35V ± 5% from a combination of DC-DC and MLDO and external board filtering.
  • Brown-out Reset (BOR) – Use the BOR module to monitor the VDD supply voltage. This module provides a more accurate trip point but is only enabled when the POR event is inactive and the bandgap reference voltage is enabled and ready. Use this module to ensure that the supply voltage is above the minimum operating voltage needed for program memory reads to be valid.
  • Zero-power BOR (ZPBOR) – Use this low-power BOR during Deep Sleep operation. The user can only enable the ZPBOR when DSZPBOR configuration bit is ‘1’.
  • Flash Low-Voltage Detect (LVD) uses PLVD.
  • Master Clear Filter (MCLRF) – NMCLR generates a device Reset request based on the state of a device input pin. To minimize the effects of noise and to avoid unwanted Reset conditions, the MCLRF function filters the input pin to assure a specific pulse duration of the low input pulse.
    Note: Ignore the nominal pulses below 400 ns.
  • Programmable Low-Voltage Detect of VDD (PLVD) consists of the following sub-modules:
    • LVD comparator
    • Resistor ladder
    • Analog voltage switch
    • LVD control (VDDCORE DOMAIN)