33.6.2.5 SPI Transfer Modes

There are four combinations of SCK phase and polarity to transfer serial data. The SPI Data Transfer modes are shown in the following table and figure.

SCK phase is configured by the Clock Phase bit in the CTRLA register (CTRLA.CPHA). SCK polarity is programmed by the Clock Polarity bit in the CTRLA register (CTRLA.CPOL). Data bits are shifted out and latched in on opposite edges of the SCK signal. This ensures sufficient time for the data signals to stabilize.

Table 33-3. SPI Transfer Modes
ModeCPOLCPHALeading EdgeTrailing Edge
000Rising, sampleFalling, setup
101Rising, setupFalling, sample
210Falling, sampleRising, setup
311Falling, setupRising, sample
Note:
  • The leading edge is the first clock edge in a clock cycle.
  • The trailing edge is the second clock edge in a clock cycle.
Figure 33-3. SPI Transfer Modes