26.6.3.3 Channel Suspend
The channel operation can be suspended at
any time by software by writing a ‘1
’ to the Suspend command in
the Command bit field of Channel Control B register (CHCTRLB.CMD). After the ongoing burst
transfer is completed, the channel operation is suspended and the suspend command is
automatically cleared.
When suspended, the Channel Suspend Interrupt flag in the Channel Interrupt
Status and Clear register is set (CHINTFLAG.SUSP=1
) and the
optional suspend interrupt is generated.
By configuring the block action to suspend by writing Block Action bit group
in the Block Transfer Control register (BTCTRL.BLOCKACT is 0x2
or
0x3
), the DMA channel will be suspended after it has
completed a block transfer. The DMA channel will be kept enabled and will be able to
receive transfer triggers, but it will be removed from the arbitration scheme.
If an invalid transfer descriptor (BTCTRL.VALID=0
) is fetched
from SRAM, the DMA channel will be suspended, and the Channel Fetch Error bit in the
Channel Status register (CHASTATUS.FERR) will be set.
For more details on transfer descriptors (see Transfer Descriptors from Related Links).