26.6.3.10 Memory CRC Monitor
When enabled, it is possible to continuously check a a memory block data integrity by calculating and checking the CRC checksum. The following table shows the expected CRC checksum value that must be located in the last memory block location.
| CRCCTRL.CRCPOLY | CRCCTRL.CRCBEATSIZE | Last Memory Block Byte Locations Value (MSB Byte First) | CHECKSUM Result |
|---|---|---|---|
| CRC-16 | Byte | Expected CRC[7:0] Expected CRC[15:8] | 0x00000000 |
| Half-word | |||
| Word | 0x00 0x00 Expected CRC[7:0] Expected CRC[15:8] | ||
| CRC-32 | Byte | Expected CRC[31:24] Expected CRC[23:16] Expected CRC[15:8] Expected CRC[7:0] | CRC Magic Number (0x2144DF1C) |
| Half-word | |||
| Word |
When the channel is enabled and the descriptor is fetched, the CRC Checksum register (CRCCHKSUM) is reloaded with the initial checksum value (CHKINIT) stored in the DSTADDR location of the first descriptor. The DMA read and calculate the checksum over the entire data from the source address. When the checksum calculation is completed, the DMA read the last beat from the memory, and the calculated CRC value from the CRC Checksum register is compared to zero or the CRC magic number depending on CRC polynomial selection.
If the CHECKSUM does not match the comparison value, the DMA channel is disabled and both the CRC Error bit in the Channel n Status register (CHSTATUSn.CRCERR) and Transfer Error interrupt flag (CHINTFLAGn.TERR) are set. If enabled, the Transfer Error interrupt is generated.
If the calculated checksum value matches the compare value, the Transfer Complete Interrupt flag (CHINTFLAGn.TCMPL) is set, optional interrupt is generated and the DMA performs the following actions depending on the descriptor list settings:
- If the list has only one descriptor, the DMA re-fetches the descriptor.
- If the current descriptor is the last descriptor from the list, the DMA fetches the first descriptor from the list.
When the fetch is completed, the DMA restarts the operations described above when new triggers are detected.
To enable the memory CRC monitor, the following actions must be performed:
- The CRC module must be set to be used with a DMA channel (CRCCTRL.CRCSRC).
- Reserve memory space addresses to configure a descriptor or a list of descriptors.
- Configure each descriptor.
- Set the next descriptor address (DESCADDR).
- In the first list descriptor, set the destination address with the initial checksum value (DSTADDR = CHKINIT).
- Set the transfer source address (SRCADDR).
- Set the block transfer count (BTCNT).
- Set the memory CRC monitor operation mode (CRCCTRL.CRCMODE = CRCMON).
- Enable optional interrupts.
- Enable the corresponding DMA channel (CHCTRLAn.ENABLE).
