28.5.3 Clocks
The CCL bus clock PB2_CLK (CLK_CCL_APB) can be enabled and disabled in the CRU.
A generic clock (GCLK_CCL) is optionally required to clock the CCL. This clock must be configured and enabled in the Generic Clock Controller (GCLK) before using input events, filter, edge detection or sequential logic. GCLK_CCL is required when input events, a filter, an edge detector or a sequential sub-module is enabled.
This generic clock is asynchronous to the user interface clock.
See Clock and Reset Unit (CRU) from Related Links.