34.6.4.1.1 Host DMA

When using the I2C host with DMA, the ADDR register must be written with the desired address (ADDR.ADDR), transaction length (ADDR.LEN) and transaction length enable (ADDR.LENEN). When ADDR.LENEN is written to ‘1’ along with ADDR.ADDR, ADDR.LEN determines the number of data bytes in the transaction from 0-255. DMA is, then, used to transfer ADDR.LEN bytes followed by an automatically generated NACK (for host reads) and a STOP.

If a NACK is received by the client for a host write transaction before ADDR.LEN bytes, a STOP is automatically generated and the length error (STATUS.LENERR) is raised along with the INTFLAG.ERROR interrupt.

The I2C host generates the following requests:
  • Write data received (RX) – The request is set when host write data is received. The request is cleared when DATA is read.
  • Read data needed for transmit (TX) – The request is set when data is needed for a host read operation. The request is cleared when DATA is written.
  • Write data received (RX) – If the FIFO is disabled, the request is set when host write data is received. If the FIFO is enabled, the request is set when the RX FIFO threshold is reached (CTRLC.RXTRHOLD). The request is cleared when DATA is read.
  • Read data needed for transmit (TX) – If the FIFO is disabled, the request is set when data are needed for a host read operation. If the FIFO is enabled, the request is set when the TX FIFO threshold is reached (CTRLC.TXTRHOLD). The request is cleared when DATA is written.