19.5 Interrupt and Reset Generation

The NMI timer provides a delay between WDT events and a device Reset. Set the delay in the System Clock counts from 0 to 255 in the NMICNT[15:0] bits (RNMICON[15:0]). If these bits are set to zero, there is no delay between the WDTO flag and a device Reset. If set to a non-zero value, the NMI interrupt has that number of system clocks to clear flags or save data for debugging purposes.

If the corresponding NMI flag (RNMICON.WDTR) is not cleared in RNMICON before the counter reaches zero, a device Reset is issued.

If the corresponding NMI flag in RNMICON is cleared before the counter reaches zero, the counter is stopped, then reloaded with the NMICNT value again and waits for another NMI event to occur. A device Reset will not be asserted in this case, and software will be able to return from this NMI interrupt.

The WDTS flag is set if there is a WDT event during the Standby Sleep/Idle mode. The WDTS flag will wake the CPU from Standby Sleep/Idle mode, but will not start the NMI counter, nor cause a Reset.

To detect a WDT Reset, the WDTO bit (RCON[4]), SLEEP bit (RCON[3]) and IDLE bit (RCON[2]) must be tested. If the WDTO bit is ‘1’, the event was due to a WDT time-out. The SLEEP and IDLE bits can, then, be tested to determine if the WDT event occurred while the device was awake or if it was in the Standby Sleep or Idle mode.