16.10.1 CoreSight Identification
A system-level ARM CoreSight ROM table is present in the device to identify the vendor and the chip identification method. Its address is provided in the MEM-AP BASE register inside the ARM debug access port. The CoreSight ROM implements a 64-bit conceptual ID composed from the PID0 to PID7 CoreSight ROM table registers. The following figure illustrates the conceptual 64-bit peripheral ID.
| Field | Size | Description | Location |
|---|---|---|---|
| JEP-106 CC code | 4 | Microchip continuation code: 0x0 | PID4 |
| JEP-106 ID code | 7 | Microchip device ID: 0x1F | PID1+PID2 |
| 4KB count | 4 | Indicates that the CoreSight component is a ROM: 0x0 | PID4 |
| RevAnd | 4 | Not used; read as ‘0’ | PID3 |
| CUSMOD | 4 | Not used; read as ‘0’ | PID3 |
| PARTNUM | 12 | Contains 0xCD0 to indicate that DSU is present | PID0+PID1 |
| REVISION | 4 | DSU revision (starts at 0x0 and increments by 1 at both major and minor revisions). Identifies DSU identification method variants. If 0x0, this indicates that device identification can be completed by reading the Device Identification register (DID) | PID2 |
For more details, refer to the ARM Debug Interface Version 5 Architecture Specification.