32.6.4.2 Interrupts

The USART has the following interrupt sources. These are asynchronous interrupts and can wake up the device from any sleep mode:

Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC)
Receive Start (RXS)
Clear to Send Input Change (CTSIC)
Received Break (RXBRK)
Error (ERROR)

Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the Interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET) and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). The status of enabled interrupts can be read from either INTENSET or INTENCLR.

An interrupt request is generated when the Interrupt flag is set and if the corresponding interrupt is enabled. The interrupt request remains active until either the Interrupt flag is cleared, the interrupt is disabled or the USART is reset. For details on clearing Interrupt flags, see INTFLAG from Related Links.

The value of INTFLAG indicates which interrupt is executed.

Note: Interrupts must be globally enabled for interrupt requests. See Nested Vector Interrupt Controller (NVIC) from Related Links.