21.8.5 Error Address

Name:	ERRADDR
Offset:	0x04
Reset:	0x00000000
Property:	Read-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
							ERRADDR[17:16]
Access							R	R
Reset							0	0


Bit	15	14	13	12	11	10	9	8
	ERRADDR[15:8]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ERRADDR[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bits 17:0 – ERRADDR[17:0] ECC Error Address

The RAM address offset from RAM start that caused an ECC error. If a single-bit error is followed by a dual-bit error, this register is updated with the address of the dual-bit error, otherwise, it stalls on the first error occurrence. This register reads as ‘0’ unless INTFLAG.SINGLEE and/or INTFLAG.DUALE are ‘1’.