21.8.4 Status

Name:	STATUS
Offset:	0x03
Reset:	0x00
Property:	Read-only


Bit	7	6	5	4	3	2	1	0
								ECCDIS
Access								R
Reset								0

Bit 0 – ECCDIS ECC Disable

This bit is fuse-updated at start-up based on the DEVCFG0/CFGCON0.FRECCDIS bit in the Boot Flash device configuration. When enabled, the calculated ECC is written to SRAM along with data. ECC correction and detection is enabled for reads. The ECCDIS bit is writable if dsu_testmode is set.

Value	Description
0	ECC detection and correction is enabled.
1	ECC detection and correction is disabled.